Analog to digital converters of the type where an unknown analog voltage is converted to a multi-bit word in successive stages, wherein the most significant bit of the word is followed by the lesser significant bits in succession, are well known. Such sequential converters may be of the successive approximation or bucket brigade types. One such converter is described in U.S. Pat. No. 4,072,938, issued Feb. 7, 1978, and is hereby incorporated by reference.
Digital accumulators or multipliers of the type where the bits are input to the multiplier in serial form, and then are sequentially processed bit by bit to obtain the product, are also well known. Although such multipliers more commonly process initially the least significant bit followed by the more significant bits in succession; it is known that they may be designed to process initially the most significant bit followed by the lesser significant bits in succession. Such sequential multipliers, which are sometimes referred to as being of the shift and add type, where the most significant partial product is added first and then shifted to the left in a shift register is referred to on page 202 of a publication entitled, "Design of Digital Computers" by Hans W. Gschwind published in 1967; and on pages 164, 177 through 180 of a publication entitled, "The Logic of Computer Arithmetic" by Ivan Flores, published in 1963.
Heretofore, in converting an analog signal to a digital multi-bit word, and then processing such bits in a digital multiplier, the analog-to-digital conversion of all of the bits of a word were first completed and then the bits were processed (multiplied) in the appropriate sequence depending upon the design of the multiplier. This, of course, caused a delay between the completion of the conversion and the completion of the weighting or multiplication of the AND output and the weighting digital word; and in many cases necessitated the use of higher speed multiplier components in order to perform the weighting function without slowing down the rate of processing.
Thus, it is desirable to be able to multiply or weight the individual bits of a word as they become available from the analog to digital converter, instead of waiting for the conversion of the complete word. This in turn would permit the use of lower speed, and thus lower cost logic components, to perform the multiplication without slowing down the processing rate.